What is FPGA?
Field-programmable gate array (FPGA) technology, such as the Xilinx
Virtex family of devices, has made inroads into space-based
platforms over the past decade. These devices have programmable
logic and routing that are used to implement user circuits and are
well-suited for the digital signal processing algorithms that are
often used in space.
Unlike radiation-hardened anti-fuse FPGAs that can only be
programmed once, radiation-tolerant devices can programmed an
unlimited number of times. The ability to reconfigure the device to
implement new circuits makes SRAM FPGAs interesting to the space
community.
Unlike other hardware devices that have the circuit fabricated into
the silicon, new circuits can be implemented on an FPGA while on
orbit. Therefore, reconfiguration can extend the usable lifetime of
the system by changing the FPGAs user circuit to meet changing
mission and science goals. We have also found that reconfiguration
opens up many avenues for pre-launch testing.
General view of Virtex-5 chips
Table 1 shows the major specifications of the Virtex-II and
Virtex-5 chips. The number of gates has traditionally been a way to
compare FPGA chips to ASIC technology, but it does not truly
describe the amount of useful logic inside an FPGA. This is one of
the reasons why Xilinx did not specify the number of gates for the
new Virtex-5 family.
| Virtex-II 1000 | Virtex-II 3000 | Virtex-5 LX30 | Virtex-5 LX50 | Virtex-5 LX85 | Virtex-5 LX110 |
System gates | 1 million | 3 million | ---- | ---- | ---- | ---- |
Slices | 5,120 | 14,336 | 4,800 | 7,200 | 12,960 | 17,280 |
Flip-flops | 10,240 | 28,627 | 19,200 | 28,800 | 51,840 | 69,120 |
LUTs | 10,240 | 28,627 | 19,200 | 28,800 | 51,840 | 69,120 |
Multipliers | 40 | 96 | 32 | 48 | 48 | 64 |
Block RAM (kb) | 720 | 1,728 | 1,152 | 1,728 | 3,456 | 4,608 |
Table1: Virtex-II and Virtex 5 Specifications
The number of each component is useful for direct comparisons
within each family; however, many of the component architectures
have been redesigned for the Virtex-5 making comparisons between
families difficult. For example, the Virtex-5 LX85 has fewer slices
than Virtex-II 3000, but the performance is greater on the
Virtex-5. Instead, it is more useful to examine the specific
features of the Virtex-5 to understand the benefits.
Common components such as flip-flops, LUTs, block RAM, and
multiplexers make up the basic logic structures on a Virtex FPGA. A
Collection of these basic structures is referred to as a slice or a
configurable logic block (CLB). The definitions of a CLB and a
slice are specific to each device family. For instance, a CLB on
the Virtex-II is four slices and each slice contains two 4-input
LUTs, two flip-flops, wide-function multiplexers, and carry logic.
On the Virtex-5, the definition of a CLB is two slices, and each
slice contains four 6-input LUTs, four flip-flops, wide-function
multiplexers, and carry logic. On the Virtex-5, these base slices
are called SLICEL. Some slices have built-in distributed RAM and
32-bit shift registers. Slices with these additions are called
SLICEM.
Slices | LUTs | Flip-Flops | Arithmetic and Carry Chains | Distributed RAM | Shift Registers |
2 | 8 | 8 | 2 | 256 bits | 128 bits |
Table 2: Components of a CLB on the Virtex-5
Two benefits of chips
Six-input LUT
With increasingly complex systems, applications requiring wider
data paths are more common. Traditional four-input LUTs have become
extremely limiting and require many levels of logic to implement
complex code. Xilinx has extended the LUT to a six-input LUT for
more capacity. The traditional four-input LUT has a truth table
capacity for 16 different combinations. The new six-input LUT
increases the truth table to 64 different combinations. For
example, consider the implementation of a simple comparison between
two 16-bit numbers.
A LUT compares each bit to determine the result, so a 16 bit number
requires 16 LUT inputs. If this operation were performed using a
four-input LUT architecture, it would require 11 LUTs and three
logic levels. With a six-input LUT architecture, the same function
uses only seven LUTs and two logic levels.
Diagonally Symmetric Interconnect
The denser Virtex-5 logic would be limited with the previous
interconnect design. There is a relationship between the amount of
logic and the amount of connectivity required by the logic block.
This is represented by Rent’s rule:
T=tgp
Where t and ρ are material constants, T is the number of terminals
(or connections at the boundaries of a logic block) and g is the
number of internal components (logic). Using the appropriate
constants Xilinx has calculated that the Virtex-5 requires 50
percent more interconnects than the previous design, the Virtex-4.
To achieve this, Xilinx implemented a radically new, diagonally
symmetric interconnect pattern.
Advanced Applications
Family Name | Advantage |
LX Platform | High-performance logic |
LXT Platform | High-performance logic with low-power serial connectivity |
SXT Platform | High-performance logic, DSP, memory-intensive applications, and
low-power serial connectivity |
FXT Platform | High-performance logic, embedded processing, memory-intensive
applications, and high-speed serial connectivity |
Table 3: Summary of Virtex 5 FPGA Families
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